The ever-increasing speed and resolution requirements of analog to digital converters (ADCs) are an accepted reality. Today's high speed ADCs are measured in hundreds of MHz, GHz, and even tens of GHz. The resolution of an ADC is often characterized by its Effective Number of Bits (ENOB). As these two requirements continue to rise, designers are forced to be more innovative and diligent in their design of ADCs. One approach is to design for speed at the cost of ENOB and employ other methods, such as periodic or continuous calibration, to achieve and maintain the required ENOB levels.
How to periodically or continuously calibrate an ADC is an entire field of research and development that has many factors affecting the choices at hand. For example, does the ADC sample signals continuously, in a periodic time-slot manner, or some other manner where continuous operation is not required? Another example is whether select portions of the ADC can be taken “off-line” to be calibrated without measurably affecting normal ADC operation. A further example is whether there is any a priori information about the input signal that can be exploited to assist in calibrating the ADC.
Therefore, improvements in the control of ADCs are desirable.